always @(posedge clkin or negedge rst) begin if (!rst) begin clk1<=0; count<=0; end else if(count==2) begin count<=0; clk1<=~clk1; end else count<=count+1; end
always @ (negedge clkin or negedge rst) begin if(!rst) begin clk2<=0; count<=0; end else if(count==1) clk2<=~clk2; end
always @ (clk1 or clk2 or rst) begin if(!rst) clkout<=0; else clkout<=clk1^clk2; endendmodule 作者: shjact 时间: 2015-12-24 03:31 AM
reg [1:0]count1,count2;
always @(posedge clkin or negedge rst) begin if (!rst) begin clk1<=0; count1<=0; end else if(count1==2) begin count1<=0; clk1<=~clk1; end else count1<=count1+1; end
always @ (negedge clkin or negedge rst) begin if(!rst) begin clk2<=0; count2<=0; end else if(count2==1) clk2<=~clk2; end