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VHDL牛人能帮我分析这个液晶显示程序吗?

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发表于 2015-8-6 09:39 AM | 只看该作者 回帖奖励 |倒序浏览 |阅读模式
我现在有个任务是用max11做液晶显示控制,我想先用1602来熟悉下液晶显示,看能显示最基本的几个数不,用vhdl写的,但是调了很多次,还是有问题,不知道是不是时序不对还是怎么的,大家能帮我分析下吗?、 晶振是24m,内部分频,关键是液晶使能LCD_E跟状态机的时间如何去定,我头大了,这个问题也许很简单,但对我这个初学者来说,真的有点难啊,一直出不来,希望有牛人帮下忙,程序我帖出来哦。
谢谢大家; 可能信号命名有些难读哦
--LCD状态机控制条件简单程序
--只显示已存入常量的几个数
--port : clk,rs,rw,e,q
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY LCD162 IS
PORT ( CLK : IN STD_LOGIC; --24M
RESET: IN STD_LOGIC;
lcd_RS : OUT STD_LOGIC;
LCD_RW : OUT STD_LOGIC;
LCD_E : OUT STD_LOGIC;
Q : OUT STD_LOGIC_VECTOR(7 downto 0));
END LCD162;
ARCHITECTURE ONE OF LCD162 IS
TYPE LCDSTATE IS(clear,setfunction,switchmode,setmode,setddram,writeram,idle ); --各个状态:
--清屏,功能设置,开关设置,显示方式设置,设置DDRAM地址,数据写入
TYPE RAM IS ARRAY(0 TO 2) OF STD_LOGIC_VECTOR(0 TO 7);
CONSTANT DIGIT : RAM:=("00110000","00110001","00110010");
signal count:std_logic_vector(19 downto 0);
signal lcd_buf:std_logic;
signal lcd_int:std_logic;
signal outbuffer:std_logic_vector(7 downto 0);
signal cnt:std_logic_vector(1 downto 0);
signal state:LCDstate;
signal lcd_en:std_logic;
signal lcd_clke:std_logic;
signal lcd_flag:std_logic;
signal lcd_bufo:std_logic;
BEGIN
process(clk,reset) --使能时序
begin
if(reset='0')then
count<=(others=>'0');
elsif(clk'event and clk='1')
then if (count>=52051)
then count<=(others=>'0');
else count<=count+1;
end if;
end if;
end process;
process(count,reset)
begin
if(reset='0')
then lcd_buf<='0';
elsif(count<26026)
then lcd_buf<='0';
else lcd_buf<='1';
end if;
end process;
process(clk)
begin
if(clk'event and clk='1')
then lcd_bufo<=lcd_buf;
end if;
end process;
process(lcd_bufo,reset)
begin
if(reset='0')
then lcd_int<='0';
elsif(lcd_bufo'event and lcd_bufo='1')
then lcd_int<=not lcd_int;
end if;
end process;

process(lcd_bufo,reset)
begin
if(reset='0')
then lcd_en<='0';
elsif(lcd_bufo'event and lcd_bufo='0')
then
lcd_en<=not lcd_en;
end if;
end process;
lcd_e<=lcd_en when lcd_flag='1' else '0';
lcd_rw <= '0';
process(lcd_int,reset)
begin
if(reset='0')
then state<=clear;
cnt<=(others=>'0');
lcd_rs<='0';
lcd_flag<='1';
outbuffer<="00000000";
elsif lcd_int'event and lcd_int='1'
then
case state is
when clear => lcd_rs<='0';
outbuffer<="00000001";
state<= setfunction;
when setfunction => lcd_rs<='0';
outbuffer<="00001000";
state<=switchmode;
when switchmode => lcd_rs<='0';
outbuffer<="00001100";
state<=setmode;
when setmode => lcd_rs<='0';
outbuffer<="00000110";
state<=setddram;
when setddram => lcd_rs<='0';
outbuffer<="10000000";
state<=writeram;
when writeram => if(cnt=3) then
state<=idle;
lcd_rs<='0';
lcd_flag<='0';
cnt<=(others=>'0');
else lcd_rs<='1';
outbuffer<=digit(conv_integer(cnt));
state<=writeram;
cnt<=cnt+1;
end if;

when idle =>
state<=idle;

when others => state<=clear;
end case;
end if;
end process;
q<=outbuffer;
END ONE;
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