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今天看到一个事例程序挺不错,但其中有一点我不明白啊,想请高手指点一下啊,感激不尽!! entity clock is Port ( seg : out std_logic_vector(7 downto 0); a : out std_logic_vector(3 downto 0);--用于选通三极管 clk : in std_logic); end clock; architecture Behavioral of clock is signal divcounter: std_logic_vector(27 downto 0); signal divclk:std_logic; signal sec_counter1:std_logic_vector(3 downto 0); signal sec_counter2:std_logic_vector(3 downto 0); signal min_counter1:std_logic_vector(3 downto 0); signal min_counter2:std_logic_vector(3 downto 0);
signal scan : std_logic_vector(8 downto 0); signal scan_clk: std_logic_vector(1 downto 0); signal SecSeg1,MinSeg1,SecSeg2,MinSeg2 : std_logic_vector(7 downto 0); begin --将原始时钟信号分频得到1s为周期的时钟信号divclk DIV_CLOCK:process(clk) begin if clk='1' and clk'event then if(divcounter>=X"17D783F")then divcounter<=X"0000000"; divclk<=not divclk; else divcounter<=divcounter+'1'; end if; end if; end process; 这是程序的一段,其中的 if(divcounter>=X"17D783F")then divcounter<=X"0000000";
这里为什么还带个X啊?是不是表示十六进制啊?我是新手,问题可能有点傻,不要见怪啊,嘿嘿,谢谢了啊!! |
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