使用V5时将一个普通的IO当作全局时钟使用了,结果在MAP时,发生错误:ERRORlace:645 - A clock IOB clock component is not placed at an optimal clock,改了系统的环境变量,加BUFG都无法解决,请问该如何解决?主程序如下:
module ad_uart(clkin,rst,sdo, DA_in,DB_in,clk1,oea,oeb,en,tbre,tsre); output tbre,tsre; output sdo ; input rst ; input clkin ; input[11:0] DA_in,DB_in; input clk1,en; output oea,oeb; wire S_time; wire[11:0] DA_out,DB_out; wire clk2; wire clk11; IBUFG IBUFG_inst ( .O(clk11), // Clock buffer output .I(clk1) // Clock buffer input ); uart_ad u1(clkin,rst,sdo,clk2,DA_out,DB_out,S_time,tbre,tsre);
sample_fifo u2(rst,DA_in,DB_in,clk11,clk2,DA_out,DB_out,oea,oeb,en,S_time); endmodule |