verilog 写的奇数分频器遇到问题，诚请大侠指点

shjact

最近在学习verilog，刚做了个奇数分频器，
用modelsim 5.7仿真波形都是OK的，
可用ISE却总是综合不了，有一个警告说clk1是常量，count就加不到2，
所以请大侠帮忙看看我的程序是不是有问题，谢谢啦！
module div (clkout,clkin,rst);

output clkout;
input clkin;
input rst;
reg clkout;
reg clk1,clk2;
reg [1:0]count;

always @(posedge clkin or negedge rst)
begin
if (!rst)
begin
clk1<=0;
count<=0;
end
else if(count==2)
begin
count<=0;
clk1<=~clk1;
end
else
count<=count+1;
end

always @ (negedge clkin or negedge rst)
begin
if(!rst)
begin
clk2<=0;
count<=0;
end
else if(count==1)
clk2<=~clk2;
end

always @ (clk1 or clk2 or rst)
begin
if(!rst)
clkout<=0;
else
clkout<=clk1^clk2;
endendmodule

shjact

reg [1:0]count1,count2;

always @(posedge clkin or negedge rst)
begin
if (!rst)
begin
clk1<=0;
count1<=0;
end
else if(count1==2)
begin
count1<=0;
clk1<=~clk1;
end
else
count1<=count1+1;
end

always @ (negedge clkin or negedge rst)
begin
if(!rst)
begin
clk2<=0;
count2<=0;
end
else if(count2==1)
clk2<=~clk2;
end

.....

.....

shjact

thanks