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我用VHDL写了一个同时对三路频率进行测频的程序(采用双精度的方法),标准频率用100MHZ(用24位计数器存放),待测频率用16位计数器存放.可在程序写完之后提示逻辑单元不够用了...请问程序应该如何修改才能尽量减少逻辑单元的使用呢? (我用的是EPM7160SCL84-6). 程序如下: library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity four0ut is port( f0,fx,fy,fz,rs,en : in std_logic; choose: in std_logic_vector (3 downto 0); output: out std_logic_vector (7 downto 0)); end four0ut; architecture behave of four0ut is signal out_fx0,out_fx1,out_fx2,out_fx3 :std_logic_vector (3 downto 0); --待测频率1计数存放 signal out_fy0,out_fy1,out_fy2,out_fy3 :std_logic_vector (3 downto 0); --待测频率2计数存放 signal out_fz0,out_fz1,out_fz2,out_fz3 :std_logic_vector (3 downto 0); --待测频率3计数存放
signal out_f00,out_f01,out_f02,out_f03,out_f04,out_f05 :std_logic_vector (3 downto 0); --待测频率1对应的标准频率计数存放 signal out_f10,out_f11,out_f12,out_f13,out_f14,out_f15 :std_logic_vector (3 downto 0); --待测频率2对应的标准频率计数存放 signal out_f20,out_f21,out_f22,out_f23,out_f24,out_f25 :std_logic_vector (3 downto 0); --待测频率3对应的标准频率计数存放
signal star1,star2,star3: std_logic; begin --**************以下是第一路频率的测量部分************************ process(fx,rs) begin if(rs='0') then star1 <= '0'; out_fx0 <="0000"; out_fx1 <="0000"; out_fx2 <="0000"; out_fx3 <="0000"; elsif(fx' event and fx = '1') then if(en='1') then if (out_fx0 = 15) then out_fx0 <="0000"; if (out_fx1 = 15) then out_fx1 <="0000"; if (out_fx2 = 15) then out_fx2 <="0000"; if (out_fx3 = 15) then out_fx3 <="0000"; else out_fx3 <= out_fx3 + 1 ; end if; else out_fx2 <= out_fx2 + 1 ; end if; else out_fx1 <= out_fx1 + 1 ; end if; else out_fx0 <= out_fx0 + 1 ; end if; star1 <= '1'; elsif(star1 ='1') then star1 <= '0'; end if; end if; end process;
--**********以下是第二路频率的测量部分**************************** process(fy,rs) begin if(rs='0') then star2 <= '0'; out_fy0 <="0000"; out_fy1 <="0000"; out_fy2 <="0000"; out_fy3 <="0000"; elsif(fy' event and fy = '1') then if(en='1') then if (out_fy0 = 15) then out_fy0 <="0000"; if (out_fy1 = 15) then out_fy1 <="0000"; if (out_fy2 = 15) then out_fy2 <="0000"; if (out_fy3 = 15) then out_fy3 <="0000"; else out_fy3 <= out_fy3 + 1 ; end if; else out_fy2 <= out_fy2 + 1 ; end if; else out_fy1 <= out_fy1 + 1 ; end if; else out_fy0 <= out_fy0 + 1 ; end if; star2 <= '1'; elsif(star2 ='1') then star2 <= '0'; end if; end if; end process;
--********以下是第三路频率的测量部分************************ process(fz,rs) begin if(rs='0') then star3 <= '0'; out_fz0 <="0000"; out_fz1 <="0000"; out_fz2 <="0000"; out_fz3 <="0000"; elsif(fz' event and fz = '1') then if(en='1') then if (out_fz0 = 15) then out_fz0 <="0000"; if (out_fz1 = 15) then out_fz1 <="0000"; if (out_fz2 = 15) then out_fz2 <="0000"; if (out_fz3 = 15) then out_fz3 <="0000"; else out_fz3 <= out_fz3 + 1 ; end if; else out_fz2 <= out_fz2 + 1 ; end if; else out_fz1 <= out_fz1 + 1 ; end if; else out_fz0 <= out_fz0 + 1 ; end if; star3 <= '1'; elsif(star3 ='1') then star3 <= '0'; end if; end if; end process;
--*************以下是标准频率的测量部分****************** process(f0,rs) begin if(rs = '0') then out_f00 <="0000"; out_f01 <="0000"; out_f02 <="0000"; out_f03 <="0000"; out_f04 <="0000"; out_f05 <="0000"; out_f10 <="0000"; out_f11 <="0000"; out_f12 <="0000"; out_f13 <="0000"; out_f14 <="0000"; out_f15 <="0000"; out_f20 <="0000"; out_f21 <="0000"; out_f22 <="0000"; out_f23 <="0000"; out_f24 <="0000"; out_f25 <="0000";
elsif(f0' event and f0 = '1') then if(star1 = '1') then if (out_f00 = 15) then out_f00 <="0000"; if (out_f01 = 15) then out_f01 <="0000"; if (out_f02 = 15) then out_f02 <="0000"; if (out_f03 = 15) then out_f03 <="0000"; if (out_f04 = 15) then out_f04 <="0000"; if (out_f05 = 15) then out_f05 <="0000"; else out_f05 <= out_f05 + 1 ; end if; else out_f04 <= out_f04 + 1 ; end if; else out_f03 <= out_f03 + 1 ; end if; else out_f02 <= out_f02 + 1 ; end if; else out_f01 <= out_f01 + 1 ; end if; else out_f00 <= out_f00 + 1 ; end if; end if; if(star2 = '1') then if (out_f10 = 15) then out_f10 <="0000"; if (out_f11 = 15) then out_f11 <="0000"; if (out_f12 = 15) then out_f12 <="0000"; if (out_f13 = 15) then out_f13 <="0000"; if (out_f14 = 15) then out_f14 <="0000"; if (out_f15 = 15) then out_f15 <="0000"; else out_f15 <= out_f15 + 1 ; end if; else out_f14 <= out_f14 + 1 ; end if; else out_f13 <= out_f13 + 1 ; end if; else out_f12 <= out_f12 + 1 ; end if; else out_f11 <= out_f11 + 1 ; end if; else out_f10 <= out_f10 + 1 ; end if; end if; if(star3 = '1') then if (out_f20 = 15) then out_f20 <="0000"; if (out_f21 = 15) then out_f21 <="0000"; if (out_f22 = 15) then out_f22 <="0000"; if (out_f23 = 15) then out_f23 <="0000"; if (out_f24 = 15) then out_f24 <="0000"; if (out_f25 = 15) then out_f25 <="0000"; else out_f25 <= out_f25 + 1 ; end if; else out_f24 <= out_f24 + 1 ; end if; else out_f23 <= out_f23 + 1 ; end if; else out_f22 <= out_f22 + 1 ; end if; else out_f21 <= out_f21 + 1 ; end if; else out_f20 <= out_f20 + 1 ; end if; end if; end if; end process; --***************以下是输出部分程序*********************** process(choose) begin case choose is --**********以下是第一组测量结果的输出*********************************** when "0000" => output(7 downto 4) <= out_f05 ; output(3 downto 0) <= out_f04 ; when "0001" => output(7 downto 4) <= out_f03 ; output(3 downto 0) <= out_f02 ; when "0010" => output(7 downto 4) <= out_f01 ; output(3 downto 0) <= out_f00 ; when "0011" => output(7 downto 4) <= out_fx3 ; output(3 downto 0) <= out_fx2 ; when "0100" => output(7 downto 4) <= out_fx1 ; output(3 downto 0) <= out_fx0 ; --************以下是第二组测量结果的输出*********************************** when "0101" => output(7 downto 4) <= out_f15 ; output(3 downto 0) <= out_f14 ; when "0110" => output(7 downto 4) <= out_f13 ; output(3 downto 0) <= out_f12 ; when "0111" => output(7 downto 4) <= out_f11 ; output(3 downto 0) <= out_f10 ; when "1000" => output(7 downto 4) <= out_fy3 ; output(3 downto 0) <= out_fy2 ; when "1001" => output(7 downto 4) <= out_fy1 ; output(3 downto 0) <= out_fy0 ; --******以下是第三组测量结果的输出*********************************** when "1010" => output(7 downto 4) <= out_f25 ; output(3 downto 0) <= out_f24 ; when "1011" => output(7 downto 4) <= out_f23 ; output(3 downto 0) <= out_f22 ; when "1100" => output(7 downto 4) <= out_f21 ; output(3 downto 0) <= out_f20 ; when "1101" => output(7 downto 4) <= out_fz3 ; output(3 downto 0) <= out_fz2 ; when "1110" => output(7 downto 4) <= out_fz1 ; output(3 downto 0) <= out_fz0 ; when others => output <= "00000000"; end case; end process; end behave;
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