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TI 公司的Stellaris LM3S2616是{方案}ARM Cortex-M3内核的32位MCU,具有32位RISC性能,有多种外设如UART,CAN等,工作频率50MHz,设计用于工业应用包罗遥控,电子POS机,测试和丈量设备,网络设备和互换,工厂自动化,HVAC和修建物控制,游戏设备,运动控制,医疗仪器以及消防和安全.本京电港论坛文章先容了 LM3S2616主要特点,方框架图,RDK-BDC24 BLDC马达控制板主要特点和指标,电路原理图纸,质料清单和PCB线路板元件结构图. The Stellaris?family of microcontrollers he first ARM?Cortex?M3 based controllers rings high-performance 32-bit computing to cost-sensitive embedded microcontroller applications. These pioneering parts deliver customers 32-bit performance at a cost equivalent to legacy 8- and 16-bit devices, all in a package with a small footprint. The Stellaris family offers efficient performance and extensive integration, favorably positioning the device into cost-conscious applications requiring significant control-processing and connectivity capabilities. The Stellaris LM3S2000 series, designed for Controller Area Network (CAN) applications, extends the Stellaris family with Bosch CAN networking technology, the golden standard in short-haul industrial networks. The Stellaris LM3S2000 series also marks the first integration of CAN capabilities with the revolutionary Cortex-M3 core. The LM3S2616 microcontroller is targeted for industrial applications, including remote monitoring, electronic point-of-sale machines, test and measurement equipment, network appliances and switches, factory automation, HVAC and building control, gaming equipment, motion control, medical instrumentation, and fire and security. For applications requiring extreme conservation of power, the LM3S2616 microcontroller features a battery-backed Hibernation module to efficiently power down the LM3S2616 to a low-power state during extended periods of inactivity. With a power-up/power-down sequencer, a continuous time counter (RTC), a pair of match registers, an APB interface to the system bus, and dedicated non-volatile memory, the Hibernation module positions the LM3S2616 microcontroller perfectly for battery applications. In addition, the LM3S2616 microcontroller offers the advantages of ARM’s widely available development tools, System-on-Chip (SoC) infrastructure IP applications, and a large user community. Additionally, the microcontroller uses ARM’s Thumb?compatible Thumb-2 instruction set to reduce memory requirements and, thereby, cost. Finally, the LM3S2616 microcontroller is code-compatible to all members of the extensive Stellaris family; providing flexibility to fit our customers’ precise needs. Texas Instruments offers a complete solution to get to market quickly, with evaluation and development boards, white papers and application notes, an easy-to-use peripheral driver library, and a strong support, sales, and distributor network. LM3S2616主要特点: The LM3S2616 microcontroller includes the following product features: ■ 32-Bit RISC Performance C32-bit ARM® Cortex™-M3 v7M architecture optimized for small-footprint embedded applications CSystem timer (SysTick), providing a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism CThumb®-compatible Thumb-2-only instruction set processor core for high code density C50-MHz operation CHardware-division and single-cycle-multiplication C Integrated Nested Vectored Interrupt Controller (NVIC) providing deterministic interrupt handling C 33 interrupts with eight priority levels C Memory protection unit (MPU), providing a privileged mode for protected operating system functionality C Unaligned data access, enabling data to be efficiently packed into memory C Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined peripheral control ■ ARM® Cortex™-M3 Processor Core CCompact core. CThumb-2 instruction set, delivering the high-performance expected of an ARM core in the memory size usually associated with 8- and 16-bit devices; typically in the range of a few kilobytes of memory for microcontroller class applications. CRapid application execution through Harvard architecture characterized by separate buses for instruction and data. CExceptional interrupt handling, by implementing the register manipulations required for handling an interrupt in hardware. CDeterministic, fast interrupt processing: always 12 cycles, or just 6 cycles with tail-chaining CExternal non-maskable interrupt signal (NMI) available for immediate execution of NMI handler for safety critical applications. CMemory protection unit (MPU) to provide a privileged mode of operation for complex applications. CMigration from the ARM7™ processor family for better performance and power efficiency. CFull-featured debug solution •Serial Wire JTAG Debug Port (SWJ-DP) •Flash Patch and Breakpoint (FPB) unit for implementing breakpoints •Data Watchpoint and Trigger (DWT) unit for implementing watchpoints, trigger resources, and system profiling •Instrumentation Trace Macrocell (ITM) for support of printf style debugging •Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer COptimized for single-cycle flash usage CThree sleep modes with clock gating for low power CSingle-cycle multiply instruction and hardware divide C Atomic operations C ARM Thumb2 mixed 16-/32-bit instruction set C 1.25 DMIPS/MHz ■ JTAG CIEEE 1149.1-1990 compatible Test Access Port (TAP) controller CFour-bit Instruction Register (IR) chain for storing JTAG instructions CIEEE standard instructions: BYPASS, IDCODE, SAMPLE/PRELOAD, EXTEST and INTEST CARM additional instructions: APACC, DPACC and ABORT CIntegrated ARM Serial Wire Debug (SWD) ■ Hibernation CSystem power control using discrete external regulator CDedicated pin for waking from an external signal CLow-battery detection, signaling, and interrupt generation C32-bit real-time clock (RTC) CTwo 32-bit RTC match registers for timed wake-up and interrupt generation CClock source from a 32.768-kHz external oscillator or a 4.194304-MHz crystal CRTC predivider trim for making fine adjustments to the clock rate C64 32-bit words of non-volatile memory CProgrammable interrupts for RTC match, external wake, and low battery events ■ Internal Memory C128 KB single-cycle flash •User-managed flash block protection on a 2-KB block basis •User-managed flash data programming •User-defined and managed flash-protection block C16 KB single-cycle SRAM CPre-programmed ROM •Stellaris family peripheral driver library (DriverLib) •Stellaris boot loader ■ DMA Controller C ARM PrimeCell® 32-channel configurable μDMA controller CSupport for multiple transfer modes •Basic, for simple transfer scenarios •Ping-pong, for continuous data flow to/from peripherals •Scatter-gather, from a programmable list of arbitrary transfers initiated from a single request CDedicated channels for supported peripherals COne channel each for receive and transmit path for bidirectional peripherals CDedicated channel for software-initiated transfers CIndependently configured and operated channels CPer-channel configurable bus arbitration scheme CTwo levels of priority CDesign optimizations for improved bus access performance between μDMA controller and the processor core •μDMA controller access is subordinate to core access •RAM striping •Peripheral bus segmentation CData sizes of 8, 16, and 32 bits CSource and destination address increment size of byte, half-word, word, or no increment CMaskable device requests COptional software initiated requests for any channel CInterrupt on transfer completion, with a separate interrupt per channel ■ GPIOs C1-33 GPIOs, depending on configuration C5-V-tolerant in input configuration CTwo means of port access: either Advanced High-Performance Bus (AHB) with better back-to-back access performance, or the legacy Advanced Peripheral Bus (APB) for backwards-compatibility with existing code CFast toggle capable of a change every clock cycle for ports on AHB, every two clock cycles for ports on APB CProgrammable control for GPIO interrupts •Interrupt generation masking • Edge-triggered on rising, falling, or both • Level-sensitive on High or Low values C Bit masking in both read and write operations through address lines C Can initiate an ADC sample sequence C Pins configured as digital inputs are Schmitt-triggered. C Programmable control for GPIO pad configuration • Weak pull-up or pull-down resistors • 2-mA, 4-mA, and 8-mA pad drive for digital communication; up to four pads can be configured with an 18-mA pad drive for high-current applications • Slew rate control for the 8-mA drive • Open drain enables • Digital input enables ■ General-Purpose Timers CFour General-Purpose Timer Modules (GPTM), each of which provides two 16-bit timers. Each GPTM can be configured to operate independently: •As a single 32-bit timer •To trigger analog-to-digital conversions C32-bit Timer modes •Programmable one-shot timer •Programmable periodic timer •User-enabled stalling when the controller asserts CPU Halt flag during debug •ADC event trigger C16-bit Timer modes •General-purpose timer function with an 8-bit prescaler (for one-shot and periodic modes only) •Programmable one-shot timer •Programmable periodic timer •User-enabled stalling when the controller asserts CPU Halt flag during debug •ADC event trigger ■ ARM FiRM-compliant Watchdog Timer C 32-bit down counter with a programmable load register C Separate watchdog clock with an enable C Programmable interrupt generation logic with interrupt masking C Lock register protection from runaway software C Reset generation logic with an enable/disable C User-enabled stalling when the controller asserts the CPU Halt flag during debug ■ ADC CSix analog input channels CSingle-ended and differential-input configurations COn-chip internal temperature sensor CSample rate of one million samples/second CFlexible, configurable analog-to-digital conversion CFour programmable sample conversion sequences from one to eight entries long, with corresponding conversion result FIFOs CFlexible trigger control •Controller (software) •Timers •Analog Comparators •PWM •GPIO CHardware averaging of up to 64 samples for improved accuracy CConverter uses an internal 3-V reference CPower and ground for the analog circuitry is separate from the digital power and ground ■ UART CFully programmable 16C550-type UART with IrDA support CSeparate 16x8 transmit (TX) and receive (RX) FIFOs to reduce CPU interrupt service loading CProgrammable baud-rate generator allowing speeds up to 3.125 Mbps CProgrammable FIFO length, including 1-byte deep operation providing conventional double-buffered interface CFIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8 Standard asynchronous communication bits for start, stop, and parity C Line-break generation and detection C Fully programmable serial interface characteristics • 5, 6, 7, or 8 data bits • Even, odd, stick, or no-parity bit generation/detection • 1 or 2 stop bit generation C IrDA serial-IR (SIR) encoder/decoder providing • Programmable use of IrDA Serial Infrared (SIR) or UART input/output • Support of IrDA SIR encoder/decoder functions for data rates up to 115.2 Kbps half-duplex • Support of normal 3/16 and low-power (1.41-2.23 μs) bit durations •Programmable internal clock generator enabling division of reference clock by 1 to 256 for low-power mode bit duration CDedicated Direct Memory Access (DMA) transmit and receive channels ■ I2C CDevices on the I2C bus can be designated as either a master or a slave •Supports both sending and receiving data as either a master or a slave •Supports simultaneous master and slave operation CFour I2C modes •Master transmit •Master receive •Slave transmit •Slave receive CTwo transmission speeds: Standard (100 Kbps) and Fast (400 Kbps) CMaster and slave interrupt generation •Master generates interrupts when a transmit or receive operation completes (or aborts due to an error) •Slave generates interrupts when data has been sent or requested by a master CMaster with arbitration and clock synchronization, multimaster support, and 7-bit addressing mode ■ Controller Area Network (CAN) C CAN protocol version 2.0 part A/B C Bit rates up to 1 Mbps C 32 message objects with individual identifier masks C Maskable interrupt C Disable Automatic Retransmission mode for Time-Triggered CAN (TTCAN) applications C Programmable Loopback mode for self-test operation C Programmable FIFO mode enables storage of multiple message objects C Gluelessly attaches to an external CAN interface through the CANnTX and CANnRX signals ■ Analog Comparators CTwo independent integrated analog comparators CConfigurable for output to drive an output pin, generate an interrupt, or initiate an ADC sample sequence CCompare external pin input to external pin input or to internal programmable voltage reference CCompare a test voltage against any one of these voltages •An individual external reference voltage •A shared single external reference voltage •A shared internal reference voltage ■ PWM CThree PWM generator blocks, each with one 16-bit counter, two PWM comparators, a PWM signal generator, a dead-band generator, and an interrupt/ADC-trigger selector COne fault input in hardware to promote low-latency shutdown COne 16-bit counter •Runs in Down or Up/Down mode •Output frequency controlled by a 16-bit load value •Load value updates can be synchronized •Produces output signals at zero and load value CTwo PWM comparators •Comparator value updates can be synchronized •Produces output signals on match CPWM generator • Output PWM signal is constructed based on actions taken as a result of the counter and PWM comparator output signals • Produces two independent PWM signals Dead-band generator • Produces two PWM signals with programmable dead-band delays suitable for driving a half-H bridge • Can be bypassed, leaving input PWM signals unmodified • PWM output enable of each PWM signal • Optional output inversion of each PWM signal (polarity control) • Optional fault handling for each PWM signal • Synchronization of timers in the PWM generator blocks • Extended PWM synchronization of timer/comparator updates across the PWM generator • Interrupt status summary of the PWM generator blocks C Can initiate an ADC sample sequence ■ QEI CPosition integrator that tracks the encoder position CVelocity capture using built-in timer CThe input frequency of the QEI inputs may be as high as 1/4 of the processor frequency (for example, 12.5 MHz for a 50-MHz system) CInterrupt generation on: •Index pulse •Velocity-timer expiration •Direction change •Quadrature error detection ■ Power COn-chip Low Drop-Out (LDO) voltage regulator, with programmable output user-adjustable from 2.25 V to 2.75 V CHibernation module handles the power-up/down 3.3 V sequencing and control for the core digital logic and analog circuits C Low-power options on controller: Sleep and Deep-sleep modes C Low-power options for peripherals: software controls shutdown of individual peripherals C 3.3-V supply brown-out detection and reporting via interrupt or reset ■ Flexible Reset Sources CPower-on reset (POR) CReset pin assertion CBrown-out (BOR) detector alerts to system power drops CSoftware reset CWatchdog timer reset CInternal low drop-out (LDO) regulator output goes unregulated ■ Industrial-range 64-pin RoHS-compliant LQFP package 1.2 Target Applications ■ Remote monitoring ■ Electronic point-of-sale (POS) machines ■ Test and measurement equipment ■ Network appliances and switches ■ Factory automation ■ HVAC and building control ■ Gaming equipment ■ Motion control ■ Medical instrumentation ■ Fire and security ■ Power and energy ■ Transportation RDK-BDC24 BLDC马达驱动参考方案 The RDK-BDC24 is a Stellaris reference design for speed control of 12 V and 24 V brushed DC motors at up to 40 A continuous current. Features include high-performance CAN and RS232 networking as well as a rich set of control options and sensor interfaces, such as analog and quadrature encoder interfaces. High-frequency PWM enables the DC motor to run smoothly and quietly over a wide speed range. The MDL-BDC24 uses highly optimized software and a powerful 32-bit Stellaris LM3S2616 microcontroller to implement open-loop speed control as well as closed-loop control of speed, position, or motor current. The Reference Design Kit (RDK-BDC24) contains an MDL-BDC24 motor control module as well as additional hardware and software for evaluating RS232 communication. After evaluating the RDK-BDC24, users may choose to either customize parts of the hardware and software design or use the MDL-BDC24 without modification. RDK-BDC24 BLDC马达控制板主要特点:
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