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STSTi7108HDAVCSTB译码方案

2017-11-24 04:38 PM| 发布者: VR孤狼| 查看: 2979| 评论: 0

摘要: ST公司的STi7108是下一代HDAVCSTB译码器,用于卫星,有线和地面电视和IP-STB市场.STi7108具有OpenGLES2.0/OpenVG1.1兼容的3D图像GPU,1080p50和1080p60视频译码,有高性能ST40-300500MHz的应用CPU和实时CPU,三个USB2.0主 ...

ST 公司的STi7108 是下一代HD AVC STB译码器,用于卫星,有线和地面电视和IP-STB市场. STi7108具有Open GL ES 2.0/Open VG 1.1兼容的3D图像GPU, 1080p50和1080p60视频译码,有高性能ST40-300 500MHz的应用CPU和实时CPU,三个USB2.0主端口,两个以太网GMAC等.本京电港论坛文章先容STi7108主要特点, 方框架图, 卫星HD 四调谐器DVR方框架图, 带DLNA服务器的有线DVR方框架图以及带媒体中心(DLNA)的BD播放器方框架图.

STi7108 is the next generation of HD, AVC set-top box decoder for satellite, cable, terrestrial and IP-STB markets.The STi7108 provides a solution for operators to specify a range of high-performance, MPEG2 /H.264 / VC-1 STBs.The STi7108 can be used with Zappers, IP clients, DVR standalone, and DVR server/home network STBs, especially where true 3D graphics is required.Content delivery is possible using broadcast or broadband networks, or both (hybrid STBs).

The STi7108 is also targeted at next generation DLNA compatible Blu-ray (BD) and HD Media players.

STi7108主要特点:

■ Open GL ES 2.0/Open VG 1.1 compatible 3D graphics GPU for enhanced EPGs/UIs

■ Dual HD (1080i/720p) video decode for PIP or mosaic support

■ 1080p50, 1080p60 video decoding

■ High-performance ST40-300 500 MHz applications CPU with Level 2 cache

■ High-performance ST40-300 500 MHz real-time CPU

■ Dual eSATA ports

■ Triple USB 2.0 host ports

■ Dual 16-bit/32-bit LMI supporting DDR2/DDR3

■ Dual Ethernet GMAC

■ Low power process and design with dynamic power management architecture

图1{京电港论坛}.STi7108方框架图

STi7108主要特点形貌:

CPUs

● Applications CPU, ST40-300, dual-issue, MMU, 32KI, 32KD caches, 500 MHz delivering >900DMIPs:

C Includes an L2 cache, 256KB, 2-way set associative

C Includes a tightly coupled vector FPU to accelerate 3D graphics transformations

● Real-time CPU for a/v real-time control and network processing offload - ST40-300,dual-issue, MMU, 32KI, 32KD caches, 500 MHz delivering >900DMIPs

● Additional ST231 CPU available for further offloading of the applications CPU with multimedia, security and networking tasks 2D Graphics acceleration

● Link list based, multi-operator 2D graphics blitter

● Supports rendering, formatting and pre-composition of 2D graphics and 3D-like user interface effects

● Up to 266 Mpixels/sec with destination alpha blending

● Tile RAM memory bandwidth saver accelerates blitter based pre-composition of virtual graphics planes before display

● Support for concurrent blitter use by applications and composition threads 3D Graphics acceleration

● True 3D graphics and 2D vector graphics acceleration engine (GPU), optimized for consumer applications

● Programmable Vertex (Geometry) processor and Fragment (Pixel) processor:

C Accelerated four times full scene anti-aliasing (4×FSAA)

C Tile based for memory bandwidth efficiency

C Supports decoded video as textures

● Compatible with industry standard APIs, OpenGL ES 1.1/2.0 and Open VG 1.0/1.1

● Rendering performance up to either 720p60 with 4×FSAA or 1080i60 with 4×FSAA(without lighting) with simple pixel shaders, and up to 720p30 with 4×FSAA with complex pixel shaders (with lighting)

Video decoding, transcoding and post processing

● Latest generation “Delta” Video Decoder with ST231 programmable CPU core:

C MPEG2, H264, VC-1/WMV9, HD or SD Advanced Video Decoding

C Provides flexibility to support other codecs for example MPEG4 Pt2, DivX SD/720p, XviD, H263 encode/decode, Real, Flash (Sorenson, ON2/VP6),AVS-SD/HD, MJPEG, Theora

C Single HD decoding up to H264 HP@L4.2 (1080p50, 1080p60), Dual HD decoding (MPEG2 MP@HL or H264 HP@L4.1), HD + SD decoding or Dual SD Decoding, PIP and Mosaic capable

● Real-time transcoding of MPEG2 SD to H264 SD/CIF/QCIF

● Advanced de-blocking, de-ringing/mosquito noise reduction of decoded MPEG2 sources, based on ST’s Digital Source Enhancer (DSE) Technology with 2D Analysis window and Texture Adaptive Filter High quality video reformatting

● Main display pipeline (HQVDP) comprising DEI, HQR, IQI:

C DEI - motion and detail adaptive spatial and temporal de-interlacing including 1080i60 >1080p60 deinterlacing. Film mode detection (FMD) supported

C HQR - high quality reformatting/resizing engine using 8-tap spline-based interpolation filters. Advanced features include built-in global sharpness, overshoot and edge adaptive controls

C IQI - image quality improvement capabilities including contrast enhancement,luma transient improvement, chroma transient improvement and peaking

● Aux video display pipeline (VDP):

C High quality H and V reformatting/resizing with sample rate conversion/filtering

C Motion and detail adaptive spatial and temporal de-interlacing. Film mode detection (FMD) supported

Display and output

● Independent Main and Aux display compositors (Video/Graphics mixing):

C Four independent graphics planes (GDPs) with H and V resize, CLUT and antiflicker filtering

C Flexibility to have three graphics planes on the Main compositor and one on the Auxiliary compositor or two graphics planes on each compositor

C Two video planes: Main Video plane and a 2nd video plane assignable for PIP or the Auxiliary display

C PIP is also possible using a graphics plane on Main compositor when the 2nd video plane is used for Auxiliary display

● Two options provided for concurrent HD and SD output of the main composition:

C HD display capture, down-conversion and auxiliary display with single graphics plane

C Symmetric assignment of two graphics planes and one video plane set on each compositor

● HDMI 1.3a* interface with HDCP copy protection. (HD/ED/SD formats up to 1080p60,high bit rate audio, deep color modes (30/36bits) and xv-YCC colorimetry pass through):

C Integrated HDMI CEC line controller

● PAL/NTSC/SECAM digital encoder

● Macrovision and Dwight Cavendish analog copy protection

● Six 10-bit DACs for component/composite analog video output (HD/ED/SD formats up to 1080i):

C DACs available for HD + SD output, or all DACs can be used for SD output with concurrent HD over HDMI

● Digital video input port (DVP), 8-bit SD, 16-bit HD formats supported

● 24-bit digital video output (DVO) for main display composition (HD/ED/SD formats)Audio

● ST231 CPU based Audio processor:

C MPEG1 I/II, MP3, Dolby Digital/DD+, MPEG4 AAC/AAC+, WMA/WMA-pro, Dolby True-HD, DTS HD Master Audio

C Multi-channel audio decoding with down-mixing

C PCM mixing with sample rate conversion

C Volume levelling

C Concurrent audio description decoding

C DD+ to DD and AAC+ to DD/DTS up-transcoding

C Audio encoding to AAC stereo or MP3 stereo for down-transcoding support

● Integrated stereo audio DAC

● 7.1-channel audio PCM output interface

● Stereo audio PCM input interface

● Independent S/PDIF output Memory interfaces

● Parallel external memory and peripheral interface (EMI):

C 16-bit data bus, five banks, addressing up to 64 MB per bank. 256 Mbytes total EMI address range

C Interface to Parallel NOR Flash, SLC NAND Flash, SRAM, and 8-,16-bit Peripherals

C Secure boot from NOR or NAND Flash

C Supports ATAPI, DVB-CI and CI-Plus host interface protocols

● High speed SPI interface:

C Secure boot from Serial Flash

Post boot read/write of Serial Flash

C Supports standard SPI, dual and quad I/O protocols

● Dual -16, 32-bit DDR2/DDR3 local memory interfaces (LMIs), each up to 533 MHz(DDR2/3-1066)Connectivity

● Triple USB 2.0 Host interfaces including PHYs

● Two e-SATA HDD interfaces

● 32-bit, 33 MHz, PCI interface, shared on EMI with access interleaving possible

● Two integrated Ethernet GMACs. Each supports: wake-on-LAN, multiple hardware address filters, 10/100 MII/RMII, Turbo-MII up to 300 Mbits/sec and GMII up to 1000 Mbits/sec.

● 8-bit, 52 MHz, SD-MMC/SDIO interface for memory cards and eMMC:

C V4.3 for eMMC flash support

C SD HC V2.0 PART A2

● Soft modem support: integrated MAFE: integrated system side DAA. (Si-Labs)Transport and security

● Front end transport stream pre-processor (STFE):

C PID filtering and transport stream merging

C Six external TS inputs

C Four internal TS paths from memory

C TS I/O routing for DVB-CI/CI-Plus, TS I/O routing for MultiStream CableCard with stream merging/demerging

C Aggregate TS processing > 480 Mbits/sec live input rate

● Transport stream processor with security co-processor (STBE)

C Multi-stream transport stream de-multiplexing from any source (Broadcast, IP Network, DVR)

C Section filtering and clock recovery

C Supports CA vendors’ latest advanced security specifications

C DVB/DES/TDES/AES/Multi-2/ICAM2.2 descrambling

C ATIS-IIF and CI-Plus descrambling

C Multi-stream AES/TDES encryption/decryption for local copy protection or network DRM schemes including SVP, DTCP-IP, WMDRM, DVB-CPCM, DivX, Marlin

DVR support

● DVR supported with HDD attachment through e-SATA or USB

● Server application supported: Multi-Stream DVR recording and playback for viewing locally (with time-shift), concurrently with playback to multiple clients

● Time-shift supported without HDD attached using stream buffering in NAND Flash attached directly through EMI or USB, SATA, SD-MMC card or e-MMC

STB peripherals, system services, package

● Two smartcards, four UARTs, seven SSC/I²C, 27 × 8 GPIO banks with alternate functions, IR Tx/Rx, UHF Rx/SCD, PWM, ILC, 4×4 key matrix scanner

● All required clocks generated on chip from PLLs and frequency synthesizers

● Reset controller, watchdog timers, real-time clock (RTC) and protected JTAG/DCU port

● Passive standby mode for lowest power consumption, and dynamic power management architecture to optimize power efficiency of active standby modes

Package - PBGA 35×35 864 balls, 1.0 mm ball pitch, 0.5 mm ball diameter

图2{京电港论坛}.STi7108 卫星HD DVR框架图

图3{京电港论坛}.STi7108 卫星HD 四调谐器DVR方框架图

图4{京电港论坛}.STi7108 带DLNA服务器的有线DVR框架图

图5{京电港论坛}.STi7108 带DLNA服务器的有线DVR方框架图

图6{京电港论坛}.STi7108 带媒体中心(DLNA)的BD播放器框架图

图7{京电港论坛}.STi7108 带媒体中心(DLNA)的BD播放器方框架图

详情请复制打开此衔接地址:
http://www.st.com/stonline/products/literature/bd/16790.pdf


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