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Cirrus公司的CS42L73是高度集成低功耗音频和电话CODEC,适用于手提设备如智能手机,条记本电脑. CS42L73具有机动的时钟架构,可接纳的基准时钟为6, 12, 24, 13, 26, 19.2, 或38.4 MHz,立体声ADC,支持两路模拟或数字MIC,四个DAC耦合到五个输出,单声道耳机放大器和1W扬声器放大器,数字音频混淆和路由, 3.00 V - 5.25 V工作电压,超低功耗,模数转换具有91dB动态范围和-85dB THD+N,DAC到线输出的动态范围97dB, -86dB THD+N.本京电港论坛文章先容了CS42L73主要特点,方框架图, 典范应用电路原理图纸和评估板CDB42L73特点, 系统框架图,电路原理图纸,PCB线路板元件结构图与CS42L73在智能手机中的应用框架图. The CS42L73 is a highly integrated, low-power, audio and telephony CODEC for portable applications such as smartphones and ultra mobile personal computers. The CS42L73 features a flexible clocking architecture, allowing the device to utilize reference clock frequencies of 6, 12, 24, 13, 26, 19.2, or 38.4 MHz, or any standard audio master clock. Up to two reference/master clock sources may be connected; either one can be selected to drive the internal clocks and processing rate of the CS42L73. Thus, multiple master clock sources within a system can be dynamically activated and de-activated to minimize system- level power consumption. Three asynchronous bidirectional serial ports (Auxiliary, Audio, and Voice Serial Ports) support multiple clock domains of various digital audio sources or destinations. Three low-latency, fast-locking, integrated high-performance asynchronous sample rate converters synchronize and convert the audio samples to the internal processing rate of the CS42L73. A stereo line input or two mono (one stereo) microphone (MIC) inputs are routed to a stereo ADC. The MIC inputs may be selectively pre-amplified by +10 or +20 dB. Two independent, low-noise MIC bias voltage supplies are also provided. A programmable gain amplifier (PGA) is applied to the inputs before they reach the ADC. The stereo input path that follows the stereo ADC begins with a multiplexer to selectively choose data from a digital MIC interface. Following the multiplexer, the data is decimated, selectively DC high-pass filtered, channelswapped or mono-to-stereo routed (fanned-out), and volume adjusted or muted. The volume levels can be automatically adjusted via a programmable Automatic Level Control (ALC) and noise gate. A digital mixer is utilized to mix and route the CS42L73’s inputs (analog inputs to ADC, digital MIC, or serial ports) to outputs (DAC-fed amplifiers or serial ports). There is independent attenuation on each mixer input for each output. The processing along the output paths from the digital mixer to the two stereo DACs includes volume adjustment and mute control. A peak-detector can be used to automatically adjust the volume levels via a programmable limiter. The first stereo DAC feeds the stereo headphone and line output amplifiers, which are powered from a dedicated positive supply. An integrated charge pump provides a negative supply. This allows a ground-centered analog output with a wide signal swing, and eliminates external DC-blocking capacitors while reducing pops and clicks. Trilevel Class-H amplification is utilized to reduce power consumption under low-signal-level conditions. Analog volume controls are provided on the stereo headphone and line outputs. The second stereo DAC feeds several mono outputs. The left channel of the DAC sources a mono, differentialdrive, speakerphone amplifier for driving the handset speakerphone. The right channel sources a mono, differential- drive, earphone amplifier for driving the handset earphone. The right channel is also routed to a mono,differential-drive, speakerphone line output, which may be connected to an external amplifier to implement a stereo speakerphone configuration when it is used in conjunction with the integrated speakerphone amplifier. The CS42L73 implements robust power management to achieve ultra-low power consumption. High granularity in power-down controls allows individual functional blocks to be powered down when unused. The internal low dropout regulator (LDO) saves power by running the internal digital circuits at half the logic interface supply voltage (VL/2). In a system with an existing high-efficiency supply at VL/2, the internal LDO may be disabled and the digital circuits powered directly by the external VL/2 supply. A high-speed I²C control port interface capable of up to 400 kHz operation facilitates register programming. The CS42L73 is available in space-saving 64-ball WLCSP and 65-ball FBGA packages for the commercial (-40° to +85°C) grade. CS42L73主要特点: Stereo ADC Ultra Low Power Consumption 3.5 mW Quiescent Headphone Playback System Features Native (no PLL required) Support for 6/12/24 MHz, 13/26 MHz, and 19.2/38.4 MHz Master Clock Rates in Add. to Typ. Audio Clock Rates Stereo Analog to Digital Features 91 dB Dynamic Range (A-wtd) Dual Digital Microphone Interface Programable Clock Rate Integer Divide by 2 or 4 of Internal MCLK Stereo DAC to Headphone Amplifier 94 dB Dynamic Range (A-wtd) Stereo DAC to Line Outputs 97 dB Dynamic Range (A-wtd) Mono DAC to Ear Speaker Amplifier High Power Output at -70 dB (0.032%) THD+N C 45 mW into 16 @ 1.8 V Mono DAC to Speakerphone Amplifier High Output Power at ≤1% THD+N Mono DAC to Speakerph. Line Output 84 dB Dynamic Range (A-wtd) Serial Ports Three Independent Serial Ports: Auxiliary, Audio, and Voice CS42L73应用: Smart Phones, UMPCs, and MIDs 评估板CDB42L73 Evaluation Board for the CS42L73 The CDB42L73 board is a dedicated platform for testing and evaluating the CS42L73, an ultralow power mobile audio and telephony CODEC. To allow comprehensive testing of CS42L73 features and performance, extensive hardware and software configurable options are available on the CDB42L73. The CDB42L73 also serves as a good component and layout reference for the CS42L73. 评估板CDB42L73主要特点: Analog Inputs
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